1. Technical Field
Devices and apparatuses consistent with the present invention relate to semiconductor devices and, more particularly, to semiconductor devices having a voltage generating circuit for generating an operation voltage of a nonvolatile semiconductor memory, and to semiconductor memory testers for testing an operation of a nonvolatile semiconductor memory.
2. Description of the Related Art
In related art semiconductor devices, and particularly in related art nonvolatile semiconductor memories, it is desirable to increase the capacity of the memory. It is also desirable to reduce the size in order to provide a device at a competitive price. Accordingly, the size of a memory cell has been reduced, circuits (such as a controller, a read only memory (ROM), and a random access memory (RAM)) of a memory system have been simplified, and an exclusive area for a memory cell has been increased. For example, programming, reading, and erasing operations of a flash memory use multiple exclusive controlled boosted voltages. These boosted voltages are generated by a pump circuit (i.e., a boosting circuit) and are supplied from the pump circuit to the flash memory at a time when the flash memory is operating.
The pump circuit includes, for example, a plurality of diodes and capacitors, and an area in a chip used by the pump circuit is greater than an area in a chip used by other circuits. On the other hand, to cope with devices such as a mobile device and the like in which an area for a memory chip on a mounting substrate is restricted, a multi-chip package (hereinafter, referred to as “MCP”) in which a plurality of memory chips are overlapped and enclosed in a package has been developed and widely used. A controller chip which controls memories is built in the MCP chip. Each of the memory chips enclosed in the MCP chip has a pump circuit. The pump circuit has a function of supplying a boosted voltage to the plurality of memory chips from a circuit. In terms of circuit configuration, it is redundant that each of the memory chips in the MCP chip has its own pump circuit. Alternatively, it has been proposed that the plurality of memory chips share one pump circuit, and that the pump circuit is provided, for example, in a controller chip. Thus, the occupying area of parts of the memory chips other than the pump circuits in a mounting substrate can be enlarged, thereby contributing to an increase in memory capacity.
On the other hand, providing the pump circuit in a controller chip presents some disadvantages. For example, in the MCP chip in which a plurality of memory chips having the same specification are enclosed in a package to embody a large-capacity package, the plurality of memory chips can share a voltage source used, for example, for a reading operation. If the pump circuit that supplies the voltage for the reading operation is removed from each of the memory chips, and is instead provided in a separate chip that is enclosed as a pump chip in the MCP chip, it is difficult to perform a pre-shipping test for the memory chips using known test systems. Accordingly, by mounting the pump chip on a test jig and actuating the pump chip at the time of testing the MCP chip, the pre-shipping test is enabled.
In a related art semiconductor circuit device described in JP-A-11-283398, a boosting circuit is connected to a power terminal of a flash electrically erasable and programmable read only memory (EEPROM) which operates with a single power source. A power source monitoring terminal for monitoring a power source selected by a power source selecting switch is provided, whereby it is possible to monitor a boosting power source at a time of testing the flash EEPROM. It is possible to determine whether a variation in operation characteristic of the flash EEPROM is due to a variation in boosting power source or due to a variation in flash EEPROM, thereby facilitating the test of the flash EEPROM body.